Senior Layout Design Engineer
Company: PEAK Technical Staffing USA
Posted on: November 22, 2022
Posted: 07/12/2022 Employment Type: Direct Placement Category:
Design Engineers Job Number: 94585 Job Description
The Senior Layout Design Engineer will have experience in Cadence
Virtuoso layout design flow and worked on high performance CMOS
layouts, including block-level and chip-level layout requirements.
Understanding of parasitic impact on circuit performance,
mask-reticle implementation is a plus. Capable of top-level floor
planning of blocks and knowledge of transistors, capacitors, and
resistors in sub-micron process.
BSEE and 8+ years or MS and 6+ years' experience in CMOS design
- Ability to communicate effectively with circuit designers and
flow down the layout design requirements
- Strong background with CAD tools such as Cadence Virtuoso,
- Thorough understanding of deep sub-micron layout designs
practices such as parasitic RC delay, signal integrity, metal
density rules, transistor, and capacitor matching
- Experience planning and implementing block-level
floor-planning, power distribution network, clock and signal
routing, analog and mixed signal transistor level layout
- Ability to resolve LVS/DRC errors
- Familiarity with CMOS semiconductor IC design
- Strong background in performing full custom analog IC
- Full custom circuit, block, and chip layout using Cadence
Virtuoso tools, Layout L/XL, and physical verification tools Assura
- Capable of customizing/generating standard cells for automated
digital design flows
- Experience with layout of custom devices (e.g., transistors,
diodes, resistors, capacitors, MEM structures)
- Conduct layout reviews to document and show that the
requirements are met, and any necessary waiver are approved
- ROIC experience a plus
ESSENTIAL PHYSICAL/MENTAL REQUIREMENTS:
Proficiency in use of computers, complex electronic equipment, oral
and written communication, interaction with vendors/colleagues, and
willingness to work in a fast-paced, deadline-driven environment.
Ability to work well in a team and independently.
Due to the type of work at the facility and certain access
restrictions, successful applicants must be a U.S. Citizen.
Due to Federal Contract requirements, this position requires
employees to be fully vaccinated against COVID-19 unless granted a
medical or religious exemption.
- Mixed Signal IC Design Engineer
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Keywords: PEAK Technical Staffing USA, Camarillo , Senior Layout Design Engineer, Engineering , Camarillo, California
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